Requirements
- MS EE/CS+5 year of experience or PhD EE/CS
- Experience of PCIe root complex and end points
- Verilog RTL logic design experience of multi-million gate ASICs
- Experience writing specifications and converting them to design
- Experience with bring up and lab debug of FPGAs prototyping and silicon
- Experience with commercial PCIe/CXL IPs such as Synopsys. Good communication with IP vendors.
Plus Skills:
- Experience in NVMe
- Knowledge of various DMA architectures
- Knowledge of next-gen interconnect fabric protocol (OpenCAPI, CXL, CCIX, GenZ)
