Job Duties:
- Understand the system requirements of the digital functions and develop specifications.
- Added new features like SRAM sleep mode into Final level Cache to save power consumption of the IP.
- Update microfracture of Final level Cache to support different industry interface like AXI, CHI and OMI etc.
- Design a stage pipe-lined microcontroller for Dram tests when before system bootup.
- Implement instruction sets of microcontrollers
- Design a Direct Memory Access unit to allow Final Level Cache to line fill and purge data to SSD or DDR5 memory.
- Microarchitecture of RTL code aimed for high performance, low area and low power design. Implement the function in Verilog or System Verilog according to specification. Perform IP level simulation and regression test with the design modules.
- Perform IP level synthesis and timing closure. Optimize the design for high performance, low area and low power.
- Support the Design Verification team by providing design insights for test plan design and test design, debugging and fixing failing test cases and writing self-checking tests as required.
- Support all design integration activities including LINT, CDC, synthesis and logical equivalence.
Requirements:
- Bachelor’s degree in EE, CS or related field, and 2 years of experience in digital logic systems or a master’s degree in the same disciplines is acceptable in lieu of the two-year experience.
Required experience or skills:
- Design of digital logic systems.
- RTL simulation and debugging.
- Tcl scripts.
- Standard Electronic Design Automation (EDA) tools: such as cadence virtuoso.
- Hardware description language: Verilog; ModelSim.
