Job Duties:
Understand the system requirements of the digital functions and develop specifications.
Microarchitecture of RTL code aimed for high performance, low area and low power design.
Implement the function in Verilog or System Verilog according to specification. Perform IP level simulation and regression test with the design modules.
Perform IP level synthesis and timing closure.
Optimize the design for high performance, low area and low power.
Support the DV team by providing design insights for test plan design and test design, debugging and fixing failing test cases and writing self-checking tests as required.
Support all design integration activities like LINT, CDC, synthesis and logical equivalence.
Requirements:
MS in Electrical Engineering and two years’ experience in ASIC design, including the experience in RTL logic design with Verilog or System Verilog, experience in the ASIC design flow with front-end tools: Synopsys VCS, Verdi and Spyglass, micro-architecture, and ASIC design skills, experience with computer architecture especially out-of-order execution, super scaler and pipeline, data hazard, cache/memory subsystem, CDC, and DDR SDRAM controller.
