Requirements:
- MS EE/CS or BS EE/CS+2 years of experience
- Deep knowledge on Computer Architecture especially: out-of-order execution, data hazard, cache/memory subsystems, and simulation tools
- Digital system designers: must have experience in design specification, microarchitecture, RTL logic implementation in Verilog
- Verification engineers: must have experience in advanced verification methodologies such as constrained random test benches, assertion, functional coverage, code coverage and UVM
- Team player and an optimist: able to work with teams in multiple office sites
Plus Skills:
- Bus protocol knowledge: ARM AMBA AXI/ACE/CHI or Intel QPI.
- Deep knowledge of DDR4, LP4, WIO2, and Cache hierarchy design and optimization of advanced memory controller
- Fluent in System Verilog, SVA, C++ or assembly language
- Experience with FPGA/emulator (Palladium/Veloce)
